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lt1812 1 1812fb typical application description 3ma, 100mhz, 750v/? operational ampli er with shutdown the lt ? 1812 is a low power, high speed, very high slew rate operational ampli? er with excellent dc performance. the lt1812 features reduced supply current, lower input offset voltage, lower input bias current and higher dc gain than other devices with comparable bandwidth. a power saving shutdown feature reduces supply current to 50a. the circuit topology is a voltage feedback ampli? er with the slewing characteristics of a current feedback ampli? er. the output drives a 100 load to 3.5v with 5v supplies. on a single 5v supply, the output swings from 1.1v to 3.9v with a 100 load connected to 2.5v. the ampli? er is stable with a 1000pf capacitive load which makes it useful in buffer and cable driver applications. the lt1812 is manufactured on linear technologys advanced low voltage complementary bipolar process. the dual version is the lt1813. for higher supply voltage single, dual and quad operational ampli? ers with up to 70mhz gain bandwidth, see the lt1351 through lt1365 data sheets. 4mhz, 4th order butterworth filter features applications n 100mhz gain bandwidth n 750v/s slew rate n 3.6ma maximum supply current n 50a supply current in shutdown n 8nv/ hz input noise voltage n unity-gain stable n 1.5mv maximum input offset voltage n 4a maximum input bias current n 400na maximum input offset current n 40ma minimum output current, v out = 3v n 3.5v minimum input cmr, v s = 5v n 30ns settling time to 0.1%, 5v step n speci? ed at 5v, single 5v supplies n operating temperature range: C40c to 85c n low pro? le (1mm) sot-23 (thinsot ? ) and s8 packages n wideband ampli? ers n buffers n active filters n video and rf ampli? cation n cable drivers n data acquisition systems l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. C + lt1812 220pf v in 665 232 47pf 232 C + lt1812 470pf 1812 ta01 v out 562 274 22pf 274 frequency (mhz) 0.1 C50 voltage gain (db) C40 C30 C20 C10 1 10 100 1812 ta02 C60 C70 C80 C90 0 10 v s = 5v v in = 600mv p-p peaking < 0.12db filter frequency response
lt1812 2 1812fb pin configuration absolute maximum ratings total supply voltage (v + to v ? ) ..............................12.6v differential input voltage (transient only, note 2) ......3v input voltage, shutdown voltage ...............................v s output short-circuit duration (note 3) ............. inde? nite operating temperature range (note 8)..... ? 40c to 85c (note 1) v ? 2 5 v + 4 ?in v out 1 top view s5 package 5-lead plastic tsot-23 +in 3 + ? t jmax = 150c,
lt1812 3 1812fb electrical characteristics symbol parameter conditions min typ max units v os input offset voltage (note 4) 0.4 1.5 mv i os input offset current 30 400 na i b input bias current C 0.9 4 a e n input noise voltage density f = 10khz 8 nv/ hz i n input noise current density f = 10khz 1 pa/ hz r in input resistance v cm = 3.5v differential 310 1.5 m m c in input capacitance 2pf v cm input voltage range (positive) input voltage range (negative) 3.5 4.2 C4.2 C3.5 v v cmrr common mode rejection ratio v cm = 3.5v 75 85 db minimum supply voltage 1.25 2 v psrr power supply rejection ratio v s = 2v to 5.5v 78 97 db a vol large-signal voltage gain v out = 3v, r l = 500 v out = 3v, r l = 100 1.5 1.0 3.0 2.5 v/mv v/mv v out maximum output swing r l = 500, 30mv overdrive r l = 100, 30mv overdrive 3.80 3.35 4.0 3.5 v v i out maximum output current v out = 3v, 30mv overdrive 40 60 ma i sc output short-circuit current v out = 0v, 1v overdrive (note 3) 75 110 ma sr slew rate a v = C1 (note 5) 500 750 v/s fpbw full power bandwidth 3v peak (note 6) 40 mhz gbw gain bandwidth product f = 200khz 75 100 mhz t r , t f rise time, fall time a v = 1, 10% to 90%, 0.1v, r l = 100 2 ns os overshoot a v = 1, 0.1v, r l = 100 25 % t pd propagation delay a v = 1, 50% v in to 50% v out , 0.1v, r l = 100 2.8 ns t s settling time 5v step, 0.1%, a v = C 1 30 ns thd total harmonic distortion f = 1mhz, v out = 2v p-p , a v = 2, r l = 500 C76 db differential gain v out = 2v p-p , a v = 2, r l = 150 0.12 % differential phase v out = 2v p-p , a v = 2, r l = 150 0.07 deg r out output resistance a v = 1, f = 1mhz 0.4 i shdn shdn pin current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) C100 0 C50 1 a a i s supply current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) 3 50 3.6 100 ma a t a = 25c, v s = 5v, v cm = 2.5v, r l to 2.5v unless otherwise noted (note 10). symbol parameter conditions min typ max units v os input offset voltage (note 4) 0.5 2.0 mv i os input offset current 30 400 na i b input bias current C1.0 4 a e n input noise voltage density f = 10khz 8 nv/ hz i n input noise current density f = 10khz 1 pa/ hz r in input resistance v cm = 1.5v to 3.5v differential 310 1.5 m m t a = 25c, v s = 5v, v cm = 0v unless otherwise noted (note 10).
lt1812 4 1812fb electrical characteristics t a = 25c, v s = 5v, v cm = 0v unless otherwise noted (note 10). symbol parameter conditions min typ max units c in input capacitance 2pf v cm input voltage range (positive) input voltage range (negative) 3.5 4 1 1.5 v v cmrr common mode rejection ratio v cm = 1.5v to 3.5v 73 82 db a vol large-signal voltage gain v out = 1.5v to 3.5v, r l = 500 v out = 1.5v to 3.5v, r l = 100 1.0 0.7 2.0 1.5 v/mv v/mv v out maximum output swing (positive) r l = 500, 30mv overdrive r l = 100, 30mv overdrive 3.9 3.7 4.1 3.9 v v maximum output swing (negative) r l = 500, 30mv overdrive r l = 100, 30mv overdrive 0.9 1.1 1.1 1.3 v v i out maximum output current v out = 3.5v or 1.5v, 30mv overdrive 25 40 ma i sc output short-circuit current v out = 2.5v, 1v overdrive (note 3) 55 80 ma sr slew rate a v = C1 (note 5) 200 350 v/s fpbw full power bandwidth 1v peak (note 6) 55 mhz gbw gain bandwidth product f = 200khz 65 94 mhz t r , t f rise time, fall time a v = 1, 10% to 90%, 0.1v, r l = 100 2.1 ns os overshoot a v = 1, 0.1v, r l = 100 25 % t pd propagation delay a v = 1, 50% v in to 50% v out , 0.1v, r l = 100 3 ns t s settling time 2v step, 0.1%, a v = C1 30 ns thd total harmonic distortion f = 1mhz, v out = 2v p-p , a v = 2, r l = 500 C75 db differential gain v out = 2v p-p , a v = 2, r l = 150 0.22 % differential phase v out = 2v p-p , a v = 2, r l = 150 0.21 deg r out output resistance a v = 1, f = 1mhz 0.45 i shdn shdn pin current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) C50 0 C20 1 a a i s supply current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) 2.7 20 3.6 50 ma a 0c t a 70c, v s = 5v, v cm = 0v unless otherwise noted (note 10). symbol parameter conditions min typ max units v os input offset voltage (note 4) 2 mv v os /t input offset voltage drift (note 7) 10 15 v/c i os input offset current 500 na i b input bias current 5 a v cm input voltage range (positive) input voltage range (negative) 3.5 C3.5 v v cmrr common mode rejection ratio v cm = 3.5v 73 db minimum supply voltage 2 v psrr power supply rejection ratio v s = 2v to 5.5v 76 db a vol large-signal voltage gain v out = 3v, r l = 500 v out = 3v, r l = 100 1.0 0.7 v/mv v/mv v out maximum output swing r l = 500, 30mv overdrive r l = 100, 30mv overdrive 3.70 3.25 v v i out maximum output current v out = 3v, 30mv overdrive 35 ma
lt1812 5 1812fb symbol parameter conditions min typ max units i sc output short-circuit current v out = 0v, 1v overdrive (note 3) 60 ma sr slew rate a v = C1 (note 5) 400 v/s gbw gain bandwidth product f = 200khz 65 mhz i shdn shdn pin current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) C150 1.5 a a i s supply current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) 4.6 150 ma a 0c t a 70c, v s = 5v, v cm = 2.5v, r l to 2.5v unless otherwise noted (note 10). symbol parameter conditions min typ max units v os input offset voltage (note 4) 2.5 mv v os /t input offset voltage drift (note 7) 10 15 v/c i os input offset current 500 na i b input bias current 5 a v cm input voltage range (positive) input voltage range (negative) 3.5 1.5 v v cmrr common mode rejection ratio v cm = 1.5v to 3.5v 71 db a vol large-signal voltage gain v out = 1.5v to 3.5v, r l = 500 v out = 1.5v to 3.5v, r l = 100 0.7 0.5 v/mv v/mv v out maximum output swing (positive) r l = 500, 30mv overdrive r l = 100, 30mv overdrive 3.8 3.6 v v maximum output swing (negative) r l = 500, 30mv overdrive r l = 100, 30mv overdrive 1.2 1.4 v v i out maximum output current v out = 3.5v or 1.5v, 30mv overdrive 20 ma i sc output short-circuit current v out = 2.5v, 1v overdrive (note 3) 45 ma sr slew rate a v = C1 (note 5) 150 v/s gbw gain bandwidth product f = 200khz 55 mhz i shdn shdn pin current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) C75 1.5 a a i s supply current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) 4.5 75 ma a C 40c t a 85c. v s = 5v, v cm = 0v unless otherwise noted (notes 8, 10). symbol parameter conditions min typ max units v os input offset voltage (note 4) 3 mv v os /t input offset voltage drift (note 7) 10 30 v/c i os input offset current 600 na i b input bias current 6 a v cm input voltage range (positive) input voltage range (negative) 3.5 C3.5 v v cmrr common mode rejection ratio v cm = 3.5v 72 db minimum supply voltage 2 v psrr power supply rejection ratio v s = 2v to 5.5v 75 db a vol large-signal voltage gain v out = 3v, r l = 500 v out = 3v, r l = 100 0.8 0.6 v/mv v/mv electrical characteristics 0c t a 70c, v s = 5v, v cm = 0v unless otherwise noted (note 10).
lt1812 6 1812fb electrical characteristics C 40c t a 85c. v s = 5v, v cm = 0v unless otherwise noted (notes 8, 10). symbol parameter conditions min typ max units v out maximum output swing r l = 500, 30mv overdrive r l = 100, 30mv overdrive 3.60 3.15 v v i out maximum output current v out = 3v, 30mv overdrive 30 ma i sc output short-circuit current v out = 0v, 1v overdrive (note 3) 55 ma sr slew rate a v = C1 (note 5) 350 v/s gbw gain bandwidth product f = 200khz 60 mhz i shdn shdn pin current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) C200 2 a a i s supply current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) 5 200 ma a C 40c t a 85c, v s = 5v, v cm = 2.5v, r l to 2.5v unless otherwise noted (notes 8, 10). symbol parameter conditions min typ max units v os input offset voltage (note 4) 3.5 mv v os /t input offset voltage drift (note 7) 10 30 v/c i os input offset current 600 na i b input bias current 6 a v cm input voltage range (positive) input voltage range (negative) 3.5 1.5 v v cmrr common mode rejection ratio v cm = 1.5v to 3.5v 70 db a vol large-signal voltage gain v out = 1.5v to 3.5v, r l = 500 v out = 2.0v to 3.0v, r l = 100 0.6 0.4 v/mv v/mv v out maximum output swing (positive) r l = 500, 30mv overdrive r l = 100, 30mv overdrive 3.7 3.5 v v maximum output swing (negative) r l = 500, 30mv overdrive r l = 100, 30mv overdrive 1.3 1.5 v v i out maximum output current v out = 3.5v or 1.5v, 30mv overdrive 17 ma i sc output short-circuit current v out = 2.5v, 1v overdrive (note 3) 40 ma sr slew rate a v = C1 (note 5) 125 v/s gbw gain bandwidth product f = 200khz 50 mhz i shdn shdn pin current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) C100 2 a a i s supply current shdn > v C + 2.0v (on) (note 11) shdn < v C + 0.4v (off) (note 11) 5 100 ma a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: differential inputs of 3v are appropriate for transient operation only, such as during slewing. large sustained differential inputs can cause excessive power dissipation and may damage the part. note 3: a heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted inde? nitely. note 4: input offset voltage is pulse tested and is exclusive of warm-up drift. note 5: slew rate is measured between 2v on the output with 3v input for 5v supplies and 2v p-p on the output with a 3v p-p input for single 5v supplies. note 6: full power bandwidth is calculated from the slew rate: fpbw = sr/2v p . note 7: this parameter is not 100% tested. note 8: the lt1812c is guaranteed to meet speci? ed performance from 0c to 70c. the lt1812c is designed, characterized and expected to meet speci? ed performance from C40c to 85c but is not tested or qa sampled at these temperatures. the lt1812i is guaranteed to meet speci? ed performance from C40c to 85c. note 9: thermal resistance varies with the amount of pc board metal conn- ected to the package. the nominal values are for short traces connected to the pins. the thermal resistance can be substantially reduced by connecting pin 2 of the 5-lead or 6-lead tsot-23 or pin 4 of the so-8 to a large metal area. note 10: for the 8-lead so and 6-lead tsot-23 parts, the electrical charac- teristics apply to the on state, unless otherwise noted. these parts are in the on state when either shdn is not connected, or shdn > v C + 2.0v. note 11: the shutdown ( shdn ) feature is not available on the 5-lead sot-23 parts. these parts are always in the on state.
lt1812 7 1812fb typical performance characteristics input bias current vs temperature input noise spectral density open-loop gain vs resistive load open-loop gain vs temperature output voltage swing vs supply voltage output voltage swing vs load current supply current vs temperature input common mode range vs supply voltage input bias current vs common mode voltage temperature (c) C50 C25 0 supply current (ma) 2 5 0 50 75 1812 g01 1 4 3 25 100 125 v s = 5v v s = 2.5v supply voltage (v) 0 v C input common mode range (v) 1.0 1.5 2.0 v + C2.0 C1.5 2 4 5 1812 g02 0.5 C1.0 C0.5 1 3 6 7 t a = 25c v os < 1mv input common mode voltage (v) C5.0 input bias current (a) C1.0 C0.5 t a = 25c v s = 5v 5.0 1812 g03 C1.5 C2.0 C2.5 0 2.5 0 temperature (c) C50 C0.6 C0.4 0 25 75 1812 g04 C0.8 C1.0 C25 0 50 100 125 C1.2 C1.4 C0.2 input bias current (a) v s = 5v v s = 2.5v frequency (hz) 10 100 1 10 i n 100 0.1 1 10 1k 10k 100k 1812 g05 t a = 25c v s = 5v a v = 101 r s = 10k e n input voltage noise (nv/ hz ) input current noise (pa/ hz ) load resistance () 100 60 open-loop gain (db) 62.5 65.0 67.5 70.0 75.0 1k 10k 1812 g06 72.5 t a = 25c v s = 5v v s = 2.5v temperature (c) C50 open-loop gain (db) 70.0 72.5 75.0 25 75 1812 g07 67.5 65.0 C25 0 50 100 125 62.5 60.0 v s = 5v v o = 3v r l = 500 r l = 100 supply voltage (v) 0 v C output voltage swing (v) 1.0 1.5 2.0 v + C2.0 C1.5 2 4 5 1812 g08 0.5 C1.0 C0.5 1 3 6 7 t a = 25c v in = 30mv r l = 100 r l = 100 r l = 500 r l = 500 output current (ma) C60 output voltage swing (v) C2.0 C1.0 C1.5 v + C0.5 20 1812 g09 2.0 1.0 1.5 0.5 v C C40 C20 0 40 60 v s = 5v v in = 30mv 85c 25c C40c
lt1812 8 1812fb typical performance characteristics settling time vs output step gain bandwidth and phase margin vs supply voltage gain vs frequency output impedance vs frequency gain bandwidth and phase margin vs temperature gain vs frequency output short-circuit current vs temperature open-loop gain and phase vs frequency gain vs frequency temperature (c) C50 output short-circuit current (ma) 110 115 120 25 75 1812 g10 105 100 C25 0 50 100 125 95 90 source sink v s = 5v settling time (ns) 0 C5 output step (v) C4 C2 C1 0 5 2 10 20 25 1812 g11 C3 3 4 1 5 15 30 35 t a = 25c v s = 5v a v = C1 r f = 500 c f = 3pf 0.1% settling frequency (hz) 10 gain (db) 20 40 60 70 10k 1m 10m 1000m 1812 g13 0 100k 100m 50 30 C10 0 phase (deg) 20 60 100 120 C20 80 40 C40 phase gain 5v 5v 2.5v 2.5v t a = 25c a v = C1 r f = r g = 500 frequency (hz) 1m C6 gain (db) C4 C2 0 2 10m 100m 500m 1812 g16 C8 C10 C12 C14 4 6 t a = 25c a v = 1 no r l v s = 2.5v v s = 5v frequency (hz) 1m 2 gain (db) 4 6 8 10m 100m 500m 1812 g17 0 C2 C4 C6 v s = 5v t a = 25c a v = 2 r l = 100 v s = 2.5v supply voltage (v) 0 gain bandwidth (mhz) phase margin (deg) 3 1812 g19 70 45 40 35 12 4 110 90 567 t a = 25c gbw r l = 500 gbw r l = 100 phase margin r l = 100 phase margin r l = 500 frequency (hz) 10k 100k 0.001 output impedance () 0.1 100 1m 10m 100m 1812 g12 0.01 1 10 a v = 100 a v = 10 a v = 1 t a = 25c v s = 5v temperature (c) C50 C25 gain bandwidth (mhz) phase margin (deg) 85 115 0 50 75 1812 g15 36 40 38 105 95 25 100 125 gbw v s = 5v gbw v s = 2.5v phase margin v s = 2.5v phase margin v s = 5v r l = 500 frequency (hz) 1 0 gain (db) 4 8 10m 100m 200m 1812 g18 C4 C8 12 t a = 25c a v = C1 v s = 5v r f = r g = 500 no r l c l = 1000pf c l = 500pf c l = 200pf c l = 100pf c l = 50pf c l = 0
lt1812 9 1812fb typical performance characteristics slew rate vs supply voltage slew rate vs supply voltage slew rate vs input level slew rate vs temperature total harmonic distortion + noise vs frequency undistorted output swing vs frequency shutdown supply current vs temperature power supply rejection ratio vs frequency common mode rejection ratio vs frequency temperature (c) C50 40 50 70 25 75 1812 g14 30 20 C25 0 50 100 125 10 0 60 shutdown supply current (a) v shdn = v C + 0.4v v s = 5v v s = 2.5v frequency (hz) 1k 10k 100k 40 power supply rejection ratio (db) 60 80 1m 10m 100m 1812 g20 20 0 100 Cpsrr +psrr t a = 25c a v = 1 v s = 5v frequency (hz) 1k 10k 100k 40 common mode rejection ratio (db) 60 80 1m 10m 100m 1812 g21 20 0 100 t a = 25c v s = 5v supply voltage (v) 0 200 slew rate (v/s) 300 500 600 700 1200 900 2 4 5 1812 g22 400 1000 1100 800 1 3 6 7 t a =25c a v = C1 v in = v s(total) /2 r f = r g = r l = 500 sr + sr C supply voltage (v) 0 200 slew rate (v/s) 300 2 4 5 1812 g23 400 500 600 1 3 6 7 t a =25c a v = C1 v in = 1v r f = r g = r l = 500 sr C sr + input level (v p-p ) 0 200 slew rate (v/s) 600 1200 2 4 5 1812 g24 400 1000 800 1 3 6 78 t a =25c a v = C1 v s = 5v r f = r g = r l = 500 sr C sr + temperature (c) C50 slew rate (v/s) 800 1000 1200 25 75 1812 g25 600 400 C25 0 50 100 125 200 0 sr C v s = 5v sr + v s = 5v sr C v s = 2.5v sr + v s = 2.5v frequency (hz) 10 100 0.001 0.002 0.005 total harmonic distortion + noise (%) 0.01 1k 10k 100k 1812 g26 a v = C1 a v = 1 t a = 25c v s = 5v v o = 2v p-p r l = 500 frequency (hz) 100k 5 output voltage (v p-p ) 6 7 8 9 1m 10m 100m 1812 g27 4 3 1 0 2 a v = C1 a v = 1 t a = 25c v s = 5v r l = 100 2% max distortion
lt1812 10 1812fb typical performance characteristics small-signal transient, a v = C1 small-signal transient, a v = 1 small-signal transient, a v = 1, c l = 1000pf large-signal transient, a v = C1 large-signal transient, a v = 1 large-signal transient, a v = 1, c l = 1000pf 2nd and 3rd harmonic distortion vs frequency differential gain and phase vs supply voltage capacitive load handling frequency (hz) C100 C70 C80 C90 C30 C40 C50 C60 1812 g28 harmonic distortion (db) 100k 10m 1m t a = 25c a v = 2 v s = 5v v o = 2v p-p 2nd harmonic 3rd harmonic r l = 100 2nd harmonic r l = 500 3rd harmonic total supply voltage (v) 4 differential phase (deg) differential gain (%) 0 0.25 t a = 25c 0.10 8 10 1812 g29 0.15 0.20 0.05 0 0.25 0.10 0.15 0.20 0.05 6 12 differential gain r l = 150 differential phase r l = 150 differential phase r l = 1k differential gain r l = 1k capacitive load (pf) 10 40 overshoot (%) 50 60 70 80 100 1000 10000 1812 g30 30 20 10 0 90 100 t a = 25c v s = 5v a v = 1 a v = C1
lt1812 11 1812fb layout and passive components the lt1812 ampli? er is more tolerant of less than ideal layouts than other high speed ampli? ers. for maximum performance (for example, fast settling) use a ground plane, short lead lengths and rf-quality bypass capacitors (0.01f to 0.1f). for high drive current applications, use low esr bypass capacitors (1f to 10f tantalum). the parallel combination of the feedback resistor and gain setting resistor on the inverting input combine with the input capacitance to form a pole that can cause peaking or even oscillations. if feedback resistors greater than 2k are used, a parallel capacitor of value c f > r g ? c in /r f should be used to cancel the input pole and optimize dynamic performance. for applications where the dc noise gain is 1 and a large feedback resistor is used, c f should be greater than or equal to c in . an example would be an i-to-v converter. input considerations each of the lt1812 ampli? er inputs is the base of an npn and pnp transistor whose base currents are of opposite polarity and provide ? rst-order bias current cancellation. because of variation in the matching of npn and pnp beta, the polarity of the input bias current can be positive or negative. the offset current does not depend on beta matching and is well controlled. the use of balanced source resistance at each input is recommended for applications where dc accuracy must be maximized. the inputs can withstand differential input voltages of up to 3v without damage and need no clamping or source resistance for protection. the device should not be used as a comparator because with sustained differential inputs, excessive power dissi- pation may result. capacitive loading the lt1812 is stable with a 1000pf capacitive load, which is outstanding for a 100mhz ampli? er. this is accomplished by sensing the load induced output pole and adding compensation at the ampli? er gain node. as applications information the capacitive load increases, both the bandwidth and phase margin decrease so there will be peaking in the frequency domain and in the transient response. coaxial cable can be driven directly, but for best pulse ? delity, a resistor of value equal to the characteristic impedance of the cable (i.e., 75) should be placed in series with the output. the other end of the cable should be terminated with the same value resistor to ground. slew rate the slew rate is proportional to the differential input voltage. highest slew rates are therefore seen in the lowest gain con? gurations. for example, a 5v output step in a gain of 10 has a 0.5v input step, whereas in unity gain there is a 5v input step. the lt1812 is tested for slew rate in a gain of C 1. lower slew rates occur in higher gain con? gurations. shutdown the lt1812 has a shutdown pin ( shdn , pin 8) for conserving power. when this pin is open or biased at least 2v above the negative supply, the part operates normally. when pulled down to v C , the supply current drops to about 50a. typically, the turn-off delay is 1s and the turn-on delay 0.5s. the current out of the shdn pin is also typically 50a. in shutdown mode, the ampli? er output is not isolated from the inputs, so the lt1812 shutdown feature cannot be used for multiplexing applications. the 50a typical shutdown current is exclusive of any output (load) current. in order to prevent load current (and maximize the power savings), either the load needs to be disconnected, or the input signal needs to be 0v. even in shutdown mode, the lt1812 can still drive signi? cant current into a load. for example, in an a v = 1 con? guration, when driven with a 1v dc input, the lt1812 drives 2ma into a 100 load. it takes about 500s for the load current to reach this value. power dissipation the lt1812 combines high speed and large output drive in a small package. it is possible to exceed the maximum junction temperature under certain conditions. maximum
lt1812 12 1812fb simplified schematic 1812 ss out +in Cin bias control r b v + v C shdn r1 300 c c r c c applications information junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) as follows: t j = t a + (p d ? v ja ) (note 9) power dissipation is composed of two parts. the ? rst is due to the quiescent supply current and the second is due to on-chip dissipation caused by the load current. the worst- case load induced power occurs when the output voltage is at 1/2 of either supply voltage (or the maximum swing if less than 1/2 supply voltage). therefore p dmax is: p dmax = (v + C v C )(i smax ) + (v + /2) 2 /r l or p dmax = (v + C v C )(i smax ) + (v + C v omax )(v omax /r l ) example: lt1812cs5 at 70c, v s = 5v, r l = 100 p dmax = (10v)(4.5ma) + (2.5v) 2 /10 0 = 108mw t jmax = 70c + (108mw)(250c/w) = 97c circuit operation the lt1812 circuit topology is a true voltage feedback ampli? er that has the slewing behavior of a current feedback ampli? er. the operation of the circuit can be understood by referring to the simpli? ed schematic. the inputs are buffered by complementary npn and pnp emitter followers that drive a 300 resistor. the input voltage appears across the resistor generating currents that are mirrored into the high impedance node. complementary followers form an output stage that buffers the gain node from the load. the bandwidth is set by the input resistor and the capacitance on the high impedance node. the slew rate is determined by the current available to charge the gain node capacitance. this current is the differential input voltage divided by r1, so the slew rate is proportional to the input. highest slew rates are therefore seen in the lowest gain con? gurations. the rc network across the output stage is bootstrapped when the ampli? er is driving a light or moderate load and has no effect under normal operation. when driving capacitive loads (or a low value resistive load) the network is incompletely bootstrapped and adds to the compensation at the high impedance node. the added capacitance slows down the ampli? er which improves the phase margin by moving the unity-gain cross away from the pole formed by the output impedance and the capacitive load. the zero created by the rc combination adds phase to ensure that the total phase lag does not exceed 180 degrees (zero phase margin) and the ampli? er remains stable. in this way, the lt1812 is stable with up to 1000pf capacitive loads in unity gain, and even higher capacitive loads in higher closed-loop gain con? gurations.
lt1812 13 1812fb s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635) package description 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 typ 5 plcs (note 3) datum a 0.09 C 0.20 (note 3) s5 tsot-23 0302 rev b pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
lt1812 14 1812fb package description s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 6 plcs (note 3) datum a 0.09 C 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
lt1812 15 1812fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) s 45 0C 8 typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
lt1812 16 1812fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 1999 lt 0909 rev b ? printed in usa related parts typical application part number description comments lt1360/lt1361/lt1362 single/dual/quad 50mhz, 800v/s, c-load ? ampli? ers 4ma supply current, 1mv max v os , 1a max i b lt1363/lt1364/lt1365 single/dual/quad 70mhz, 1000v/s, c-load ampli? ers 50ma output current, 1.5mv max v os , 2a max i b lt1395/lt1396/lt1397 single/dual/quad 400mhz current feedback ampli? ers 4.6ma supply current, 800v/s, 80ma output current lt1806 325mhz, 140v/s rail-to-rail i/o op amp low noise 3.5nv/ hz lt1809 180mhz, 350v/s rail-to-rail i/o op amp low distortion C90dbc at 5mhz lt1813 dual 3ma, 100mhz, 750v/s operational ampli? er dual version of the lt1812 c-load is a trademark of linear technology corporation. single 5v supply 10ms/s 12-bit adc buffer 470pf C + v in 2v p-p 2.5v dc 68 lt1812 ltc1420 12 bits 10ms/s 1812 ta03

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